`timescale 1ns / 1ns

module data_cal (
    input clk,
    input rst,
    input [15:0] d,
    input [1:0] sel,

    output [4:0] out,
    output validout
);

    reg [3:0] data_a[3:0];
    reg [4:0] out_reg = 0;

    always @(posedge clk) begin
        if (sel == 0) begin
            data_a[0] <= d[3:0];
            data_a[1] <= d[7:4];
            data_a[2] <= d[11:8];
            data_a[3] <= d[15:12];
            out_reg   <= 0;
        end else begin
            out_reg <= data_a[0] + data_a[sel];
        end
    end

    assign validout = (sel != 0);
    assign out = out_reg;

endmodule
